137 lines
7 KiB
Nix
137 lines
7 KiB
Nix
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{ lib }:
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rec {
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# gcc.arch to its features (as in /proc/cpuinfo)
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features = {
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# x86_64 Generic
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# Spec: https://gitlab.com/x86-psABIs/x86-64-ABI/
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default = [ ];
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x86-64 = [ ];
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x86-64-v2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" ];
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x86-64-v3 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "avx" "avx2" "fma" ];
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x86-64-v4 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "avx" "avx2" "avx512" "fma" ];
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# x86_64 Intel
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nehalem = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" ];
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westmere = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" ];
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sandybridge = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ];
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ivybridge = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ];
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haswell = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ];
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broadwell = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ];
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skylake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ];
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skylake-avx512 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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cannonlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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icelake-client = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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icelake-server = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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cascadelake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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cooperlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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tigerlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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alderlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ];
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# x86_64 AMD
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btver1 = [ "sse3" "ssse3" "sse4_1" "sse4_2" ];
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btver2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ];
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bdver1 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "fma" "fma4" ];
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bdver2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "fma" "fma4" ];
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bdver3 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "fma" "fma4" ];
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bdver4 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "fma" "fma4" ];
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znver1 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "fma" ];
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znver2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "fma" ];
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znver3 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "fma" ];
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znver4 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "avx512" "fma" ];
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# other
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armv5te = [ ];
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armv6 = [ ];
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armv7-a = [ ];
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armv8-a = [ ];
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mips32 = [ ];
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loongson2f = [ ];
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};
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# a superior CPU has all the features of an inferior and is able to build and test code for it
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inferiors = {
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# x86_64 Generic
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default = [ ];
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x86-64 = [ ];
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x86-64-v2 = [ "x86-64" ];
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x86-64-v3 = [ "x86-64-v2" ] ++ inferiors.x86-64-v2;
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x86-64-v4 = [ "x86-64-v3" ] ++ inferiors.x86-64-v3;
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# x86_64 Intel
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# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
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nehalem = [ "x86-64-v2" ] ++ inferiors.x86-64-v2;
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westmere = [ "nehalem" ] ++ inferiors.nehalem;
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sandybridge = [ "westmere" ] ++ inferiors.westmere;
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ivybridge = [ "sandybridge" ] ++ inferiors.sandybridge;
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haswell = lib.unique ([ "ivybridge" "x86-64-v3" ] ++ inferiors.ivybridge ++ inferiors.x86-64-v3);
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broadwell = [ "haswell" ] ++ inferiors.haswell;
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skylake = [ "broadwell" ] ++ inferiors.broadwell;
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skylake-avx512 = lib.unique ([ "skylake" "x86-64-v4" ] ++ inferiors.skylake ++ inferiors.x86-64-v4);
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cannonlake = [ "skylake-avx512" ] ++ inferiors.skylake-avx512;
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icelake-client = [ "cannonlake" ] ++ inferiors.cannonlake;
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icelake-server = [ "icelake-client" ] ++ inferiors.icelake-client;
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cascadelake = [ "cannonlake" ] ++ inferiors.cannonlake;
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cooperlake = [ "cascadelake" ] ++ inferiors.cascadelake;
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tigerlake = [ "icelake-server" ] ++ inferiors.icelake-server;
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# CX16 does not exist on alderlake, while it does on nearly all other intel CPUs
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alderlake = [ ];
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# x86_64 AMD
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# TODO: fill this (need testing)
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btver1 = [ ];
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btver2 = [ ];
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bdver1 = [ ];
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bdver2 = [ ];
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bdver3 = [ ];
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bdver4 = [ ];
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# Regarding `skylake` as inferior of `znver1`, there are reports of
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# successful usage by Gentoo users and Phoronix benchmarking of different
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# `-march` targets.
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#
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# The GCC documentation on extensions used and wikichip documentation
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# regarding supperted extensions on znver1 and skylake was used to create
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# this partial order.
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#
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# Note:
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#
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# - The successors of `skylake` (`cannonlake`, `icelake`, etc) use `avx512`
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# which no current AMD Zen michroarch support.
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# - `znver1` uses `ABM`, `CLZERO`, `CX16`, `MWAITX`, and `SSE4A` which no
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# current Intel microarch support.
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#
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# https://www.phoronix.com/scan.php?page=article&item=amd-znver3-gcc11&num=1
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# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
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# https://en.wikichip.org/wiki/amd/microarchitectures/zen
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# https://en.wikichip.org/wiki/intel/microarchitectures/skylake
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znver1 = [ "skylake" ] ++ inferiors.skylake; # Includes haswell and x86-64-v3
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znver2 = [ "znver1" ] ++ inferiors.znver1;
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znver3 = [ "znver2" ] ++ inferiors.znver2;
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znver4 = lib.unique ([ "znver3" "x86-64-v4" ] ++ inferiors.znver3 ++ inferiors.x86-64-v4);
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# other
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armv5te = [ ];
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armv6 = [ ];
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armv7-a = [ ];
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armv8-a = [ ];
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mips32 = [ ];
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loongson2f = [ ];
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};
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predicates = let
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featureSupport = feature: x: builtins.elem feature features.${x} or [];
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in {
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sse3Support = featureSupport "sse3";
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ssse3Support = featureSupport "ssse3";
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sse4_1Support = featureSupport "sse4_1";
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sse4_2Support = featureSupport "sse4_2";
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sse4_aSupport = featureSupport "sse4a";
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avxSupport = featureSupport "avx";
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avx2Support = featureSupport "avx2";
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avx512Support = featureSupport "avx512";
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aesSupport = featureSupport "aes";
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fmaSupport = featureSupport "fma";
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fma4Support = featureSupport "fma4";
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};
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}
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